On-chip learning on a new neural processing chip

Type: MSc master thesis / Long project

Neuromorphic spiking neural network chips hold great promises for edge-computing AI applications. This project involves testing and characterizing novel on-chip learning circuits in a spiking neural network hardware architecture.

ALIVE (Always-on Learning with Various Synapses) is a prototype chip whose objective is to learn from the streaming data in an online and always on manner. It consists of two crossbar-like arrays with corresponding analog and digital synapses incorporating two different learning rules. The aim is to test new error-based learning circuits implemented on the chip, and evaluate their capabilities in a single layer network. The errors are generated on-chip by analog circuits that compare the output of the chip with a target that is given as input to the chip. One of the two implemented learning rules are inspired from the cortical circuits and the other one is inspired by error-based learning rules in neural networks. Each of the two neural cores include 4 neurons, each with 64 synapses (plastic and non-plastic). Moreover, the learning circuits for each rule are connected to pads to be tested directly and more easily.

Task:
The goal of this project is to test the ALIVE chip and run learning experiments on it. The chip will be tested using a Printed Circuit Board (PCB) designed for this specific purpose, with the necessary instruments (Oscilloscope, Keithley SMU) and a computer to send the commands by the user. To send the commands to the chip, the computer talks to a 4.1 Teensy microcontroller which in turn controls the communication protocol to the ALIVE chip. The communication scheme is based on Address Event Representation (AER) used to communicate events to and from the chip to the outside world [1,2,3]. To characterize the building blocks on the chip, test circuits have been placed outside of the array and connected directly to the pads. Through connecting these pads to Digital to Analog Converters (DACs), we can change the biasing and characterize the analog circuit blocks. The outputs can be read out through the Oscilloscope.

Steps:
1. Gain a good understanding of the design and functionality of the ALIVE chip: The student will familiarize herself/himself with the design of ALIVE chip and its PCB.
2. Test the functionality of the PCB electronically: The student will perform electric tests on the PCB to ensure its functionality. Characterize the test circuit blocks electronically and find the optimum biases in the real chip compared to the simulations.
3. Characterize the array through performing simple learning experiments: Observe the weight evolution during a simple error-based learning task. Provide high and low teacher and observe the weight evolution of one synapse.
4. Run more complex learning experiments with SNN software simulations (Optional).

Starting date:
From Mid-February/Beginning of March onwards

References:
1) S. Deiss et al., “Address-event asynchronous local broadcast protocol,” 1994. [Online].
2) K. Boahen, “Point-to-point connectivity between neuromorphic chips using address-events,” IEEE Trans. Circuits Syst. II, vol. 47, no. 5,pp. 416–34, May 2000.
3) S. Moradi, N. Qiao, F. Stefanini and G. Indiveri, "A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)," in IEEE Transactions on Biomedical Circuits and Systems, vol. 12, no. 1, pp. 106-122, Feb. 2018, doi: 10.1109/TBCAS.2017.2759700.

Requirements

Bachelor's degree and/or Master's degree in Electrical engineering.

Contact

Melika Payvand
Senior Scientist Institute of Neuroinformatics
melika (at) ini.uzh.ch

Giacomo Indiveri
Professor Institute of Neuroinformatics
giacomo (at) ini.uzh.ch

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