Master’s thesis in designing low-power and low-area sensing circuitry for resistive memory devices

Resistive memory devices have been emerging as plausible candidates to implement synaptic weights and connectivity of neural networks on AI hardware. This is thanks to their non-volatile, multi-states and in-memory computing capabilities. To interface VLSI systems with such promising technology, analog sensing front-end circuitry is required.
As the size of the neural networks grow on chip, we need to design such sensing circuitries with low power and low-area footprint, while having the precision to detect the multiple states of the memory devices.
In this master's thesis, the student will investigate three topologies for reading resistive memory for integration into neuromorphic systems. The student will optimize each topology to the measurement data from HfO2 based resistive memory integrated into 130nm technology.